 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ir3513z page 1 may 11, 2009 datasheet xphase3 tm pol control ic description the ir3513z control ic provides overall c ontrol of a scalable number of phases along with an internal gate driver, current sense/sharing, and pwm. this allows the ir3513z to implement a stand-alone single-phase regulator or interface with additional phase ics to develop a power soluti on with any number of phases. with this arrangement, the final solution requires only 1 ic per phase to deploy 1 to x phases. other approaches require a control ic plus 1 to x driver ics or scalable ?all-in-one? ics th at do not utilize all ic pins or circuitry leading to increased so lution cost and siz e. features ? 0.8v reference supports 0.8v to 5.1v output voltage with +/-0.5% system set point accuracy ? dynamic margin function provides 5 % reference offset ? 1 (stand-alone) to x phase operation with additional phase ic ? programmable 250 khz to 9 mhz daisy-chain digital phase timing provides a per phase switching frequency of 250 khz to 1.5 mhz with no external components ? differential remote sense amplifier with 100kohm input impedance ? ic bias linear regulator control with programmable output voltage and uvlo ? programmable converter current limit during soft- start, hiccup with delay during normal operation ? over voltage protection communicated to phase ics ? system over voltage signal protects against failures such as a shorted high side mosfet ? detection and protection of open remote sense lines ? open control loop protection ? 7v/2a gate drivers (4a gatel sink current) ? integrated boot-strap synchronous pfet ? small thermally enhanced 32l 5 x 5mm mlpq package application circuit figure 1 - ir3513z application circuit
ir3513z page 2 may 11, 2009 ordering information ? samples only pin description device package order quantity ir3513zmtrpbf 32 lead mlpq (5 x 5 mm body) 3000 per reel * IR3513ZMPBF 32 lead mlpq(5 x 5 mm body) 100 piece strips pin# pin symbol pin description 1 gateh high-side driver output and i nput to gatel non-overlap comparator. 2 boost supply for high-side driver. an inter nal bootstrap synchronous pfet is connected between this pin and the vccp pin. 3 vccp supply for low-side driver. an inter nal bootstrap synchronous pfet is connected from this pin to the boost pin. 4 gatel low-side driver output and i nput to gateh non-overlap comparator. 5 pgnd return for low side driver and reference for gateh non-overlap comparator. 6, 24 lgnd local ground for internal circuitry and the ic substrate connection. 7 csin+ non-inverting input to the current se nse amplifier and input to debug comparator. 8 csin- inverting input to the current sense am plifier and input to synchronous rectification disable comparator. 9 enable enable input. a logic low applied to this pin puts the ic into fault mode. do not float this pin as the logic state will be undefined. 10 pg open drain output that drives low du ring startup and under any external fault condition. connect external pull-up. 11 margin tri-state input with internal pull-up to 1.425 v. low/high voltage shifts the error amplifier reference voltage up/down 5%. v(margin) should not be biased to a voltage greater than v(vccl). 12 vosen- inverting remote sense amplifier input. connect to ground at the load. 13 vosen+ non-inverting remote sense amplifier input. connect to output at the load. 14, 28 vccl output of the voltage regulator, powe r input for clock oscillator circuitry and other internal circuitry. connect a decoupling capacitor to lgnd. 15 vout remote sense amplifier output. 16 ovsns over voltage sense input during normal operation. 17 fb inverting input to the error amplifier. 18 eaout output of the error amplifier. 19 iin average current input signal from active and inactive phase ic(s). this pin is also used to communicate an over voltage condition to the phase ic(s). 20 ocset an external resistor tied to vref along with a fixed internal current source programs the constant output current limit and hiccup over-current thresholds. over-current protection can be disabled by programming the threshold higher than the possible signal on the iin pin, but no gr eater than 5v (do not float this pin). 21 vref reference voltage for the error amplifier. an external rc network to lgnd programs the margin slew rate and compensates the internal buffer amp. 22 ss/del an external capacitor to lgnd programs converter star tup and over current protection delay timing. it is also used to compensate the constant output current loop during soft start. ir3513z page 3 may 11, 2009 pin description continued 23 rosc/ovp a resistor to lgnd to program the oscillator frequency and the ocset bias current. oscillator frequency equals the phase switch ing frequency. the pin voltage is 0.6v during normal operation and higher than 1.6v if over-voltage condition is detected. 25 clkout frequency is equivalent to the phase switching frequency multiplied by the number of phases. connect to clki n pins of phase ics. 26 phsout phase timing output switching at the pha se frequency. connect to phsin pin of the first phase ic. 27 phsin feedback input of the phase timing clock. connect to the phsout pin of the last phase ic. 29 vcclfb non-inverting input of the voltage regul ator error amplifier. output voltage of the regulator is programmed by a resistor divider connected to vccl. 30 vccldrv output of the vccl regulator error ampl ifier to control an external transistor. the pin senses the input of the power supply through a resistor at power-up. 31 vcc power input for under voltage lockout (uvlo) detection and supply for internal ic circuits. 32 sw return for high-side driver and reference for gatel non-overlap comparator. ir3513z page 4 may 11, 2009 absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. operating junction temperature?????..0 to 150 o c storage temperature range???????.-65 o c to 150 o c msl rating???????????????2 reflow temperature???????????.260 o c note: maximum gateh ? sw = 8v, maximum boost ? gateh = 8v pin # pin name v max v min i source i sink 1 gateh 34v -0.3vdc, -5v for 100ns 3a for 100ns, 100ma dc 3a for 100ns, 100ma dc 2 boost 34v -0.3v 1a for 100ns, 100ma dc 3a for 100ns, 100ma dc 3 vccp 8v -0.3v n/a 5a for 100ns, 200ma dc 4 gatel 8v -0.3vdc, -5v for 100ns 5a for 100ns, 200ma dc 5a for 100ns, 200ma dc 5 pgnd 0.3v -0.3v 5a for 100ns, 200ma dc n/a 6, 24 lgnd n/a n/a 20ma 1ma 7 csin+ 8v -0.5v 1ma 1ma 8 csin- 8v -0.5v 1ma 5ma 9 enable 3.5v -0.3v 1ma 1ma 10 pg vccl + 0.3v -0.3v 1ma 20ma 11 margin 8v -0.3v 1ma 1ma 12 vosen- 1.0v -0.5v 5ma 1ma 13 vosen+ 8v -0.5v 5ma 1ma 14, 28 vccl 8v -0.3v 1ma 25ma 15 vout 8v -0.3v 5ma 25ma 16 ovsns 8v -0.3v 1ma 1ma 17 fb 8v -0.3v 1ma 1ma 18 eaout 8v -0.3v 25ma 10ma 19 iin 8v -0.3v 5ma 1ma 20 ocset 8v -0.3v 1ma 1ma 21 vdac 3.5v -0.3v 1ma 1ma 22 ss/del 8v -0.3v 1ma 1ma 23 rosc/ovp 8v -0.3v 5ma 1ma 25 clkout 8v -0.3v 100ma 100ma 26 phsout 8v -0.3v 10ma 10ma 27 phsin 8v -0.3v 1ma 1ma 29 vcclfb 3.5v -0.3v 1ma 1ma 30 vccldrv 10v -0.3v 1ma 50ma 31 vcc 18v -0.3v 1ma 1ma 32 sw 34v -0.3v dc, -5v for 100ns 3a for 100ns, 100ma dc n/a ir3513z page 5 may 11, 2009 recommended operating co nditions for reliable o peration with margin 4.75v vccl 7.5v, 4.75v vccp 7.5v, 8v vcc 16v, -0.3v vosen- 0.3v, 0 o c t j 125 o c, 7.75 k ? r osc 50 k ? electrical characteristics the electrical characteristics involve the spread of val ues guaranteed within the recommended operating conditions. typical values represent the median values, which are related to 25c. 7.75k ? r osc 50.0 k ? , c ss/del = 0.1 f +/- 10%, c gateh = 3.3nf, c gatel = 6.8nf (unless otherwise specified). parameter test condition min typ max unit vref reference margin = open 796 800 804 mv margin = 0v 755 760 765 mv system set-point accuracy (per test circuit in fig. 2) margin = vccl 835 840 845 mv source & sink currents include ocset current 50 88 116 a margin low 0.475 0.575 0.675 v margin input thresholds margin high 2.1 2.2 2.3 v margin float voltage 1.325 1.425 1.55 v margin pull-up resistor 3 4 6 k ? oscillator rosc voltage 0.575 0.600 0.625 v clkout high voltage i(clkout)=-10ma, measure v(vccl)? v(clkout) 1 v clkout low voltage i(clkout)= 10ma 1 v clkout phase delay measure time from clkin < 1v to gateh > 1v 40 75 125 ns phsout frequency r osc =50.0 k ? 225 250 275 khz phsout frequency r osc =24.5 k ? 450 500 550 khz phsout frequency r osc =7.75 k ? 1.35 1.50 1.65 mhz phsout high voltage i(phsout)= -1ma 1 v phsout low voltage i(phsout)= 1ma 1 v phsin threshold voltage compare to v(vccl) 30 50 70 % enable input threshold voltage enable rising 815 850 885 mv threshold voltage enable falling 765 800 835 mv hysteresis 25 50 75 mv bias current 0v v(enable) 3.3v -5 0 5 a blanking time noise pulse < 100ns will not register an enable state change. note 1 75 250 400 ns ir3513z page 6 may 11, 2009 parameter test condition min typ max unit over-current comparator input offset voltage 1v v(ocset) 3.3v -70 -40 -10 mv ocset bias current -5% 605 / rosc(k ? ) +5% a over-current delay counter rosc = 7.75 k ? (phsout=1.5mhz) 4096 cycle over-current delay counter rosc = 15.0 k ? (phsout=800khz) 2048 cycle over-current delay counter rosc = 50.0 k ? (phsout=250khz) 1024 cycle over-current limit amplifier input offset voltage -10 0 15 mv transconductance note 1 0.50 1.00 1.75 ma/v sink current 35 55 75 ua unity gain bandwidth note 1 0.75 2.00 3.00 khz over voltage detection (ovd) comparator threshold offset rising compare to v(vref) 60 85 105 mv threshold offset falling com pare to v(vref) -15 5 25 mv threshold hysteresis 55 70 80 mv propagation delay to iin measure time from v(vout) > v(vref) (250mv overdrive) to v(iin) transition to > 0.9 * v(vccl). 90 180 ns iin pull-up resistance 5 20 ? ovsns input bias current 0v v(ovsns) v(vccl), -1 0 1 a over voltage protection (ovp) comparator ovp threshold step v(ishare) up until gatel drives high. compare to v(vccl) -1.0 -0.8 0 v propagation delay v(vccl)=5v , step v(ishare) up from v(dacin) to v(vccl). measure time to v(gatel)>4v. 0 40 70 ns propagation delay to rosc measure time from v(vo) > v(vdac) (250mv overdrive) to v(rosc/ovp) transition to >1v. note 1. 90 300 ns ovp rosc high voltage measure v(vccl)-v(rosc/ovp) 0 0.5 1.2 v remote sense differential amplifier unity gain bandwidth note 1 3.0 6.4 9.0 mhz input offset relative to [v(vosen+) - v(vosen-)]. 1.5v v(vosen+) - v(vosen-) 5.5v 0.5v v(vosen+) - v(vosen-) 1.5v -0.2 -3 0 0 0.2 3 % mv source current 0.5v v(vosen+) - v(vosen-) 5.5v 0.5 1.0 1.7 ma sink current vout=0.5v vout=5.5v 1 11 4 25 9 34 ma slew rate note 1 2 4 8 v/us input impedance 63 100 185 k ? vosen+ input voltage range v(vccl)=7v 5.5 v high voltage v(vccl) ? v(vo) 0.03 0.1 v low voltage v(vccl)=7v 250 mv ir3513z page 7 may 11, 2009 parameter test condition min typ max unit soft start and delay start delay 1.0 2.2 3.5 ms soft start time 0.9 1.5 4.5 ms pg delay 0.4 1.3 3.8 ms oc delay time v(iin) ? v(ocset) = 500 mv 75 125 300 us ss/del to fb input offset voltage with fb = 0v, adjust v(ss/del) until eaout drives high 0.7 1.4 1.9 v charge current 30 50 65 a discharge current 2 4 6 a charge/discharge current ratio 10 12 17 a/ a charge voltage 2.8 3 3.3 v delay comparator threshold relative to charge voltage, ss/del rising ? note 1 80 mv delay comparator threshold relative to charge voltage, ss/del falling ? note 1 120 mv delay comparator hysteresis note 1 30 mv discharge comparator threshold 125 200 275 mv error amplifier input offset voltage measure v(fb) ? v(vref). note 2 -1 0 1 mv fb bias current -1 0 1 a dc gain note 1 100 110 120 db bandwidth note 1 20 30 40 mhz slew rate note 1 7 12 20 v/ s sink current 0.40 0.85 1.00 ma source current 5 8 12 ma maximum voltage measure v(vccl) ? v(eaout) 500 780 950 mv minimum voltage 120 250 mv open voltage loop detection threshold measure v(vccl) - v(eaout), relative to error amplifier maximum voltage. 100 500 1000 mv open voltage loop detection delay measure phsout pulse numbers from v(eaout) = v(vccl) to pg = low. 8 pulses headroom control activation voltage v(vcc) ? v(csin-) 2.7 2.95 3.3 v fb bias current v(vcc) ? v(csin-) = 1.0v -640 -470 -300 ua pg comparator threshold -18.5 -13.5 -9 ua pg comparator hysteresis 5 8 13.5 ua vcc under voltage lockout comparator (uvlo) start threshold 6.9 7.4 7.9 v stop threshold 6.5 7.0 7.5 v hysteresis start ? stop 350 450 650 mv ir3513z page 8 may 11, 2009 parameter test condition min typ max unit open sense line detection sense line detection active comparator threshold voltage 150 200 250 mv sense line detection active comparator offset voltage v(vout) < [v(vosen+) ? v(lgnd)] / 2 40 60 90 mv vosen+ open sense line comparator threshold compare to v(vccl) 87.5 90 92.5 % vosen- open sense line comparator threshold 0.36 0.40 0.44 v sense lines detection source currents v(vout) = 100mv 250 500 750 ua vccl regulator amplifier reference feedback voltage 1.15 1.19 1.23 v vcclfb bias current -1 0 1 ua vccldrv sink current 10 30 ma uvlo start threshold compare to v(vccl) 90 94 98 % uvlo stop threshold compare to v(vccl) 82 86 90 % hysteresis compare to v(vccl) 7.0 8.5 9.5 % gate drivers gateh source resistance boost ? sw = 7v. note 1 1.0 2.5 ? gateh sink resistance boost ? sw = 7v. note 1 1.0 2.5 ? gatel source resistance vccp ? pgnd = 7v. note 1 1.0 2.5 ? gatel sink resistance vccp ? pgnd = 7v. note 1 0.4 1.0 ? gateh source current boost=7v,gateh=2.5v,sw=0v. note 1 2.0 a gateh sink current boost= 7v,gateh=2.5v,sw=0v. note 1 2.0 a gatel source current vccp=7v, gatel=2.5v, pgnd=0v note 1 2.0 a gatel sink current vccp=7v, gatel=2.5v, pgnd=0v note 1 4.0 a gateh rise time boost ? sw = 7v, measure 1v to 4v transition time 5 10 ns gateh fall time boost - sw = 7v, measure 4v to 1v transition time 5 10 ns gatel rise time vccp ? pgnd = 7v, measure 1v to 4v transition time 10 20 ns gatel fall time vccp ? pgnd = 7v, measure 4v to 1v transition time 5 10 ns gatel low to gateh high delay boost = vccp = 7v, sw = pgnd = 0v, measure time from gatel falling to 1v to gateh rising to 1v 10 20 40 ns gateh low to gatel high delay boost = vccp = 7v, sw = pgnd = 0v, measure time from gateh falling to 1v to gatel rising to 1v 10 20 40 ns disable pull-down resistance ta=25 o c note 1 80 130 k ? ir3513z page 9 may 11, 2009 parameter test condition min typ max unit pwm comparator pwm ramp slope 42 52.5 57 mv/ dc% input offset voltage note 1 -5 0 5 mv minimum pulse width note 1 65 75 ns minimum gateh turn-off time 20 80 160 ns current sense amplifier csin+/- bias current -200 0 200 na csin+/- bias current mismatch note 1 -50 0 50 na input offset voltage csin+ = csin- = vref. measure input referred offset from vref -1 0 1 mv gain csin+=25mv+csin- 30.5 33.0 35.5 v/v unity gain bandwidth c(iin )=10pf. measure at iin. note 1 4.8 6.8 8.8 mhz slew rate note 1 6 v/ s differential input range -10 50 mv differential input range -5 50 mv common mode input range -0.2 note3 v rout at t j = 25 o c note 1 2.3 3.0 3.7 k ? rout at t j = 65 o c 2.9 3.7 4.6 k ? rout at t j = 125 o c 3.6 4.7 5.4 k ? ishare source current 500 a ishare sink current 500 a share adjust amplifier input offset voltage note 1 -3 0 3 mv differential input range note 1 -1 1 v gain csin+ = csin- = vref, adjust v(iin) from v(ramp floor) ? 10mv to v(ramp floor) + 10mv and measure change in pwm ramp start voltage. note 1. 4 5.0 6 v/v unity gain bandwidth note 1 4 8.5 17 khz maximum pwm ramp adjust voltage csin+ = csin- = vref, eaout =lgnd, and v(iin) = v(ramp floor) - 100mv. maximum adjust voltage =v(pwmrmp) ? v(ramp floor) 90 150 250 mv minimum pwm ramp adjust voltage csin+ = csin- = vref, eaout =lgnd, and v(ishare) = v(ramp floor) + 100mv. minimum adjust voltage = v(pwmrmp) ? v(ramp floor) -230 130 -70 mv body brake comparator threshold voltage increasing compare to v(ramp floor) -225 -125 -25 mv threshold voltage decreasing compare to v(ramp floor) -315 -215 -115 mv threshold hysteresis 40 90 140 mv propagation delay vccl = 5v. measure time from eaout < v(vref) (200mv overdrive) to gatel transition to < 4v. 20 40 70 ns ir3513z page 10 may 11, 2009 note 1: guaranteed by design, but not tested in production note 2: vref output is trimmed to compensate for error & remote sense amp input offsets note 3: vccl-0.5v or vcc ? 2.5v, whichever is lower parameter test condition min typ max unit synchronous rectification disable comparator threshold voltage the ratio of v(csin-) / v(vref), below which v(gatel) is always low. 63 75 89 % negative current comparator input offset voltage note 1 -16 0 16 mv propagation delay time apply step voltage to v(csin+) ? v(csin-). measure time to v(gatel)< 1v. 200 400 ns bootstrap diode forward voltage i(boost) = 30ma, 6v vccl 7v 180 260 470 mv debug comparator threshold voltage compare to v(vccl) -260 -150 -60 mv pg output output voltage i(pg) = 4ma 150 300 mv leakage current v(pg) = 5.5v 0 10 a vcc pg activation threshold i(pg)=4ma, v(pg)<300mv 1 2 3.5 v output under voltage comparator threshold voltage falling 0.600 0.665 0.730 v threshold voltage rising 0.660 0.715 0.770 v threshold hysteresis 20 50 90 mv general vcc supply current v(vcc) ? v( vout) > 2.5v 1.1 3.0 6.1 ma vccl supply current 9 14 19 ma vccp supply current v(vccp)=7v, v(boost)=7v 50 150 300 ua boost supply current 4v v ( boost) 30v 1.2 3.5 5.8 ma sw floating voltage measured in the application 0.3 v ir3513z page 11 may 11, 2009 system set point test + - cvref rrosc + - rvref + - ocset vref rosc eaout fb vout lgnd vosen- vosen+ irosc eaout vosns- iocset- 50k 50k + - 1k 50k 50k vref buffer amplifier iocset current source generator rosc buffer amplifier 0.6v internal vref isink isource remote sense amplifier error amplifier irosc ir3513 system set point voltage figure 2 - system set point test circuit ir3513z page 12 may 11, 2009 system theory of operation pwm control method the pwm block diagram of the xphase tm architecture is shown in figure 3. feed-forward voltage mode control with trailing edge modulation is used. a voltage-type error amplif ier with high-gain (110db) and wide-bandwidth is used for the control loop. it is not unity gain stable. the power-st age input voltage is sensed by the ir3513z, and optional phase ics, to provide feed-forward control. the pwm ramp slope will change with the input voltage and automatically compensate for changes in the input voltage. the input vo ltage can change due to variations in the silver box output voltage or due to the wire and pcb-trace voltage drop related to changes in load current. vosns+ vosns- clkout control bus to additional phases power bus to additional phases ic bias pwm comparator pwm comparator - + + + ramp discharge clamp enable phsout body braking comparator pwm latch current sense amplifier r s share adjust error amplifier reset dominant phase ic remote sense amplifier ccs rcs cfb + - rcs cbst + - ccs + - cbst + - + - ccomp rfb1 + - rfb 3k + - clk d q + - + - + - rcomp 3k + - + - ccomp1 clk d q + - vref vo gnd vout remote sense - remote sense + vcc gateh lgnd ishare eaout csin- csin+ gatel vccl vcch sw vin fb pgnd ishare phsin dacin vcc clkin vcch csin- csin+ gatel eain gateh phsin phsout sw pgnd vccl vid6 vid6 vid6 vid6 vid6 vid6 vid6 vid6 vid6 vid6 + - + + ramp discharge clamp enable vref body braking comparator clock generator dominant pwm latch current sense amplifier error amplifier r s share adjust error amplifier reset ir3513 control ic cout figure 3 - pwm block diagram frequency and phase timing control the oscillator system clock frequency is programmable from 500 khz to 9 mhz by an external resistor. the ir3513z system clock signal (clkout) is connected to clkin of all the phase ics. the phase timing of the phase ics is controlled by the daisy chain loop, wh ere the ir3513z phase clock output (phs out) is connected to the phase clock input (phsin) of the first phase ic, and phsout of the first phase ic is connected to phsin of the second phase ic, etc. the last phase ic (phsout) is connected back to phsin of the control ic to complete the loop . during power up, the ir3513z sends out clock signals from both clkout and phsout pins and detects the feedback at phsin pin to determine the phase number and monitor any fault in the daisy chain loop. figure 4 shows the phase timing for a four- phase converter. for single-phase operation, phsout (pin 26) and phsin (pin 27) must be shorted together to prevent an open control loop fault from occurring. ir3513z page 13 may 11, 2009 phase ic1 pwm latch set control ic clkout (phase ic clkin) control ic phsout (phase ic1 phsin) phase ic 1 phsout (phase ic2 phsin) phase ic 2 phsout (phase ic3 phsin) phase ic 3 phsout (phase ic4 phsin) phase ic4 phsout (control ic phsin) figure 4 - five phase oscillator waveforms pwm operation upon receiving the falling edge of a clock pulse, the pwm latc h is set; the pwm ramp voltage begins to increase; the low side driver is turned off, and the high side driver is then turned on afte r the non-overlap time . when the pwm ramp voltage exceeds the error amplifier?s out put voltage the pwm latch is reset. this turns off the high side driver and then turns on the low side driver after the non-overlap time and activates the ramp discharge clamp. the ramp discharge clamp quickly discharges the pwm ramp capacitor to the out put voltage of the share adjust amplifier in the phase ic until the next clock pulse . the pwm latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. phases can overlap an d go up to 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. an erro r amplifier output voltage greater than the common mode input range of the pwm comparator results in up to 100% duty cycle regardless of the voltage of the pwm ramp. this arrangement guarantees the error amplifier is always in c ontrol and can demand 0 to 100% duty cycle as required. it also favors response to a load step decrease, which is appro priate given the low output to input voltage ratio of most systems. the inductor current will increase much more r apidly than decrease in response to load transients. an additional advantage of the architecture is that differences in ground or input voltage at the phases have no effect on operation since the pwm ramps are referenced to vref. figure 5 depicts pwm operating wave forms under various conditions. ir3513z page 14 may 11, 2009 figure 5 - pwm operating waveforms body braking tm in a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; o min max slew v i i l t ) ( * ? = the slew rate of the inductor current can be significantly in creased by turning off the synchronous rectifier in response to a load step decrease. the switch node voltage is t hen forced to decrease until conduction of the synchronous rectifier?s body diode occurs. this increases the vo ltage across the inductor from vout to vout + v bodydiode . the minimum time required to reduce the current in the induc tor in response to a load transient decrease is now; bodydiode o min max slew v v i i l t + ? = ) ( * since the voltage drop in the body diode is often higher than the output voltage, the inducto r current slew rate can be increased by 2x or more. this patent pending technique is re ferred to as ?body braking? and is accomplished through the ?body braking comparator?. if the error amplifier?s out put voltage drops below the vref voltage or a programmable voltage, this comparator turns off the low side gate driver. lossless average inductor current sensing inductor current can be sensed by connect ing a series resistor and a capacitor network in parallel with the inductor and measuring the voltage across the capacitor, as shown in figure 6. the equation of the sensing network is, cs cs l l cs cs l c c sr sl r s i c sr s v s v + + = + = 1 ) ( 1 1 ) ( ) ( usually the resistor rcs and capacitor c cs are chosen so that the time cons tant of rcs and ccs equals the time constant of the inductor which is the inductance l over the inductor dcr (r l ). if the two time constants match, the voltage across ccs is proportional to the current through l, and the sense ci rcuit can be treated as if only a sense resistor with the value of r l was used. the mismatch of the time constants does not affect the measurement of inductor dc current, but affects the ac component of the inductor current. ir3513z page 15 may 11, 2009 figure 6 - inductor current sens ing and current sense amplifier the advantage of sensing the inductor curre nt versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. the output voltage can be positioned to meet a load line based on real time inform ation. except for a sense resistor in series with the inductor, this is the only sense method that can support a single cycle transient response. other methods provide no information during either load increase (low side sensing) or load decrease (high side sensing). an additional problem associated with peak or valley current m ode control for voltage positioning is that they suffer from peak-to-average errors. these errors will show in many ways but one example is the effect of frequency variation. if the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. variations in inducta nce, current sense amplifier bandwidth, pwm prop delay, any added slope compensation, input voltage, and output voltage are all additional sources of peak-to-average errors. current sense amplifier a high speed differential current sense amplifier is included in both the ir3513z and optional phase ics, as shown in figure 6. its gain is nominally 33 at 25oc, and the 3850 ppm/oc increase in induc tor dcr should be compensated in the voltage loop feedback path. the current sense amplifier c an accept positive differential input up to 50mv and negative up to -10mv before clipping. the output of the current sense amplifier is summed with the vref voltage and sent to other phases through an on- chip 3k ? resistor connected to the ishare pin. the ishare pins of all the phas es are tied together and the voltage on the share bus represents the average current through all t he inductors and is used by the control ic for voltage positioning and current limit protection. the input offset of this amplifier is calibr ated to +/- 1mv in order to reduce the current sense error. the input offset voltage is the primary source of error for t he current share loop. in order to achieve very small input offset error and superior current sharin g performance, the current sense amplifier continuously calibrates itself. this calibration algorithm creates ripple on is hare bus with a frequency of fsw/896. average current share loop current sharing between phases of the c onverter is achieved by the average cu rrent share loop in each phase ic. the output of the current sense amplifier is compared with average current at the shar e bus. if current in a phase is smaller than the average current, the share adjust amplifier of the phase will pull down t he starting point of the pwm ramp thereby increasing its duty cycle and output current; if current in a phase is larger than the average current, the share adjust amplifier of the phase will pull up the starting point of the pwm ramp thereby decreasing its duty cycle and output current. the current share amplifier is internally compensated so that the crossover frequency of the current share loop is much slower than that of the voltage loop and the two loops do not interact. c l r l r cs c cs v o current sense amp csout i l v l v cs c ir3513z page 16 may 11, 2009 ir3513z theory of operation block diagram the ir3513z block diagram is shown in figure 7, and sp ecific features are discussed in the following sections. + - ov under voltage monitor 400k headroom control 0v@start en en disable vccl uvlo oc after vrrdy oc before vrrdy detection pulse vccl uvlo open daisy chain vcc vcc uvlo open sense line iin headroom contr reset fault latch1 ov open sense line vccl uvlo open daisy chain eaout reset vccl uvlo vccl s r q + - + - + - + - + - + - + - 2.2v vccl-0.5v + - + - + - + - 50k 50k ov s r q + - 50k + - + - + - + - + - s r q + - + - 50k pg ss/del margin vccldrv vcclfb clkout vcc enable fb eaout vref vosen- vosen+ vccl vout ovsns iin ocset vccl vccl vccl s r q reset dom gatel enable latch vid4 phsout irosc oc irosc oc disable ivosen- vidsel hr reset vdacfast irosc vid0 vid0 odc hr delay comparator 3.2v margin input comparators 4.5ua enable comparator error amplifier 0.575v 850mv 800mv vref buffer amplifier internal vref -200mv -100mv 100% dc limit oscillator (4 phase application waveform shown) 250ns blanking vcc vccl output comparator vccl regulator amplifier 1.19v idchg reset dominant vr ready latch remote sense amplifier 0.94 0.86 0.2v discharge comparator 80mv 120mv oc delay counter ivosen+ 200mv 0.4v vccl*0.9 ivosen- soft start clamp iocset oc limit comparator 1.4v ov comparator 85mv 5mv 4 open sense line detect comparators 60mv uvlo comparator 7.4v 7.0v + - 2.95v headroom control amplifier oc limit amplifier + - uv cleared fault latch2 set dominant ss cleared fault latch1 + - detection pulse set dominant s r q isource isink 300mv + - + - 8-pulse delay + - clk r d q q 3k internal circuit bias s r q + - + - clk d q open control loop comparator boost lgnd gateh csin+ vccp csin- gatel pgnd rmpout phsin phsout sw pwm reset vcc calibration calibration calibration irosc debug off phsin vccl irosc current sense amplifier body braking comparator pwm comparator pwm latch share adjust amplifier - 1v x33 1v synchronous rectification disable comparator + + + pwm ramp generator ovp comparator gatel non- overlap comparator gatel driver gateh driver gatel non- overlap latch gateh non- overlap latch set dominant (low=open) reset dominant x 0.75 debug comparator set dominant 150mv gateh non- overlap comparator negative current comparator 0.8v dacin-share_adj eain vid4 iocset- irosc 1.425v 4k 0.8v + - vref=0.84v csin- + - + - vref=0.76v + - + - + rosc/ovp 0.6v rosc buffer amplifier current source generator open control loop 0.897x 0v inv figure 7 - block diagram ir3513z page 17 may 11, 2009 vref control the margin input comparators monitor the margin pin an d control the internal reference voltage whose output is sent to the vref buffer amplifier. the output of the buffer am plifier is the vref pin. the vref voltage, input offsets of error amplifier and remote sense differential amp lifier are post-package trimmed to provide 0.8% system set-point accuracy. the actual vref voltage does not determine t he system accuracy, which has a wider tolerance. the ir3513z can accept changes in the margin input while operating and vary the vref voltage accordingly. the slew rate of the voltage at the vref pin can be adjusted by an external capacitor between vref pin and lgnd pin. a resistor connected in series with this capacitor is required to compensate the vref buffer amplifier. margin transitions result in a smooth analog transition of the vref voltage and converter output voltage minimizing inrush currents in the input and output capacitors and ov ershoot of the output voltage. remote voltage sensing vosen+ and vosen- are used for remote sensing and are connected directly to the load. the remote sense differential amplifier with high speed, low input offset and low input bias current ensures accurate voltage sensing and fast transient response. start-up sequence the ir3513z has a programmable soft-start function to limit t he surge current during the converter start-up. a capacitor connected between the ss/del and lgnd pins controls soft start timing, over-current protection delay and hiccup mode timing. a charge current of 52.5ua (t ypical) and discharge current of 4.5ua (typical) control the up and down slope of the voltage at the ss/del pin respectively. figure 8 shows normal converter start-up. if there is no fault, the ss/del pin w ill start charging. the error amplifier output eaout is clamped low until ss/del reaches 1.4v. the error amplifier will then regulate the converter?s output voltage to match the ss/del voltage, less the 1.4v offset, unt il the converter output reache s the level determined by the vref (0.8 v typically) inputs. the ss/de l voltage continues to increase until it rises above 3.12v and allows the pg signal to be asserted. ss/del finally settles at 3.2v indicating the end of the soft start. vccl under voltage lock out, over current, as well as a low sig nal on the enable input immediately sets the fault latch, which causes the eaout pin to drive low turning off the phase ic drivers. the pg pin also drives low, and ss/del begins to discharge until the voltage reache s 0.2v. if the fault has cleared the f ault latch will be reset by the discharge comparator allowing a normal soft start to occur. other fault conditions, such as over voltage, open sense lin es, and open daisy chain, set different fault latches, which start discharging ss/del, pull down eaout voltage and drive pg low. however, the latches can only be reset by cycling vccl power. if ss/del pin is pulled below 0.7v, the converter can be disabled. ir3513z page 18 may 11, 2009 figure 8 - start-up sequence constant over-current control during soft start the over-current limit threshold is set by a resistor connected between ocset and vref pins. if the iin pin voltage, which is proportional to the average current plus vref voltage, exceeds the ocset voltage during soft start, the constant over-current control is activated. figure 9 shows the constant over-current control with delay during soft start. the delay is required since over-current conditions can occur as part of normal operation due to inrush current. if an over-current occurs during soft start (before pg is as serted), the ss/del voltage is re gulated by the over current amplifier to limit the output current below the threshold set by ocset voltage. if the over-cu rrent condition persists after the delay time is reached, the fault latch will be set pulling t he error amplifier?s output low and inhibiting switching in the phase ics. the ss/del capacitor will discharge until it reache s 0.2v and the fault latch is reset allowing a normal soft start to occur. if an over-current condi tion is again encountered during the soft start cycle, the cons tant over-current control actions will repeat and the converter will be in hiccup mo de. the delay time is controlled by a counter, which is triggered by the oscillator. the counter values vary with sw itching frequency per phase in order to have a similar delay time for different switching frequencies. over-current hiccup protection after soft start the over current limit threshold is set by a resistor connected between ocset and vref pins. figure 9 shows the constant over-current control with delay after pg is asse rted. the delay is required since over-current conditions can occur as part of normal operation due to load transients or margin transitions. if the iin pin voltage, which is proportional to the averag e current plus vref voltage, exceeds the ocset voltage after pg is asserted, it will initiate the disc harge of the capacitor at ss/del. if the over-current condition persists long enough for the ss/del capacitor to discharge below the 120mv offset of the delay compar ator, the fault latch will be set pulling the error amplifier?s output low and inhibiting switching in the phase ics and de-asserting the pg signal. the output current is not controlled during the delay time. the ss/del capacitor will discharge until it reaches 200 mv and the fault latch is reset allowing a normal soft start to occur. if an ove r-current condition is again en countered during the soft start cycle, the over-current action will repeat and the converter will be in hiccup mode. 3.12v start delay vcc enable 1.4v vout pg ss/del normal operation vref 3.2v 0.8v soft start time pg delay time eaout ir3513z page 19 may 11, 2009 over-current protection (output shorted) normal operation 3.08v ea hiccup over-current protection (output shorted) power-down ocp delay start-up with output shorted normal operation 3.12v ss/del iout vout vrrdy 1.4v enable ocp threshold 3.2v normal start-up (output shorted) normal start-up figure 9 - constant over-c urrent control waveforms during and after soft start linear regulator output (vccl) the ir3513z has a built-in linear regulator controller, and only an external npn transistor is needed to create a linear regulator. the output voltage can be programmed between 4.75 v and 7v by the resistor divider at vcclfb pin. the regulator output powers the gate drivers of the phase ics and circuits in the c ontrol ic, and the voltage is usually programmed to optimize the converter efficiency. the linear regulator can be compensated by a 4.7uf capacitor at the vccl pin. as with any linear regulator, due to stability reason s, there is an upper limit to the maximum capacitor value that can be used at this pin and it is a function of the num ber of phases used in the multiphase architecture and their switching frequency. figure 10 sh ows the stability plots for the linear regulator with 5 phases switchi ng at 750 khz. figure 10 - vccl regulator stability with 5 phases and phsout equals 750 khz ir3513z page 20 may 11, 2009 vccl under voltage lockout (uvlo) the ir3513z ic monitors both the vcc and vccl for under voltage condition. during power up, the fault latch will be reset if vccl is above 94% (typical) of the voltage set by resistor divider at vcclfb pin and the vcc exceeds 7.5v (typical). if vccl voltage drops below 86% (t ypical) of the set value or vcc drops bel ow 7v (typical), the fault latch will be set. power good (pg) the pg pin is an open-collector output and should be pulled up to a voltage source through a resistor. during soft start, the pg remains low until the output voltage is in regulation and ss/del is above 3.12v. the pg pin becomes low if the fault latch, over voltage latch, open sense line latch, or open dai sy chain latch is set. a high level at the pg pin indicates that the converter is in operation and has no fault, but doe s not ensure the output voltage is within the specification. output voltage regulation within the design limits can logica lly be assured however, assuming no component failure in the system. open voltage loop detection the output voltage range of error amplifier is detected all the time to ensure the voltage loop is in regulation. if any fault condition forces the error amplifier output above vccl-0.3v for 8 switching cycles, the fault latch is set. the fault latch can only be cleared by cycling power to vccl. load current indicator output the iin pin voltage represents the average cu rrent of the converter plus the vref voltage. the load current information can be retrieved by a differential amplifier whic h subtracts the vref voltage from the iin voltage. enable input pulling the enable pin below 0.8v sets the fault latch and a voltage above 0.85v enables the soft start of the converter. over voltage protection (ovp) output over-voltage can occur during norm al operation if a high side mosfet short or other failure occurs. the over- voltage protection comparator monitors the ovsns pin volt age. if the ovsns pin voltage exceeds vref by 85mv, as shown in figure 11, the rosc/ovp pin voltage is driven to v(vccl) - 1v sending an over voltage signal to the host system. the rosc/ovp pin can also be connected to a crowba r circuit, which pulls the converter input low in over voltage conditions. the over voltage condition also sets the over voltage fault latch, which pulls the error amplifier output low to turn off the converter output. at the same time iin pin (ishare of phase ics) is pulled up to vccl to communicate the over voltage condition to phase ics (if present), as shown in figu re 11. the ovp circuit overrides the normal pwm operation and will fully turn-on the low side mosfet within approximately 150ns. the low side mosfet will remain on until ishare pin voltage drops below v(vccl) - 800mv, which sig nals the end of over voltage co ndition. an over voltage fault condition is latched in the ir3513z and can only be cleared by cycling power to vccl. in the event of a high side mosfet s hort before power up, the ovp flag is activated with as little supply voltage as possible, as shown in figure 12. the ovsn pin is comp ared against a fixed voltage of 1.73v (typical) for ovp conditions at power-up. the rosc/ovp pin will be pulled hi gher than 1.6v with vccldrv voltage as low as 1.8v. an external mosfet or comparator should be used to disable th e silver box, activate a crowbar, or turn off the supply source. the 1.8v threshold is used to prevent false over-vol tage triggering caused by pre-charging of output capacitors. ir3513z page 21 may 11, 2009 after ovp vref + 85mv ovsns ovp threshold fault latch ovp condition normal operation iin (ishare) vccl-800 mv gateh gatel error amplifier output (eaout) vref figure 11 over-voltage protection during normal operation vccl+0.7v vccl+0.7v rosc/ovp ovsn 12v vccldrv vccl uvlo 1.6v vcc 1.8v figure 12 - over-voltage pr otection during power-up ir3513z page 22 may 11, 2009 pre-charging of the converter output vo ltage may trigger ovp. if the converter output is pre-charged above 1.73v as shown in figure 17, rosc/ovp pin voltage will be hi gher than 1.6v when vccldrv voltage reaches 1.8v. rosc/ovp pin voltage will be vccldrv-1v and rise with vccldrv voltage until vccl is above uvlo threshold, after which rosc/ovp pin voltage will be vccl-1v. the conver ter cannot start unless the over voltage condition stops and vccl is cycled. if the converter output is pre-charged 130mv above vref but lower than 1.73v, as shown in figure 17, the converter will soft start un til ss/del voltage is above 3.92v (4.0v- 0.08v). then, over voltage comparator is activated and fault latch is set. rosc/ovp output voltage (vosen+) 1.8v 1.6v vccldrv vccl uvlo vcc 12v vccl+0.7v vccl+0.7v 1.73v figure 13 - over-voltage protection with pr e-charging converter output vo > 1.73v figure 14 - over-voltage protection with pre-chargi ng converter output vref + 0.13v ir3513z page 24 may 11, 2009 fault table the fault table below describes the different faults that can occur and how ir3513z would react to protect the supply and the load from possible damage. the faul t types that can occur are listed in ro w 1. row 2 has the method that a fault is cleared. the first 4 faults are latched in the uv fault la tch and the vccl power has to be recycled by switching off the input and switching it back on for the converter to work again. the rest of the faults (except for uvlo vout) are latched in the ss fault latch and do not need to recycle the vccl powe r in order for ir3513z to resume operation. ir3513z will automatically resume operation when these fault conditions no lo nger apply in the system. most of the faults disable the error amplifier (ea) and discharge the soft start capacitor. all the faults flag pgood. pgood returns back to high when the faults are cleared. the delay row show s how long it takes ir3513z to react after detecting a fault condition. delays are provided to minimize the possibility of nuisance faults. fault table fault type open daisy open control loop open sense line over voltage disable vcc uvlo vccl uvlo oc before start-up oc after start-up vout uvlo fault clearing method recycle vccl resume normal operation when condition clears error amp disabled yes no rosc/ovp & iin drive high until ov clears no yes no ss/del discharge yes no flags pgood yes delay? 30 clock pulses 8 phsout pulses no no 250 ns blank time no phsout pulses. count programm ed by rosc value ss/del discharge threshold no ir3513z page 25 may 11, 2009 applications information figure 15 - scalable master (ir3513z) & slave (ir3 505z) pol modules with programmable output voltage and redundant ovp sense ir3513z page 26 may 11, 2009 design procedures ir3513z external components oscillator resistor rosc the oscillator of ir3513z generates square-wave pulses to synchronize the phase ics. the switching frequency of the each phase converter equals the phsout frequenc y, which is set by the external resistor r osc according to the curve in figure 16. the clkout frequency equals the switching frequency multiplied by the phase number. ir3513 frequency vs. rosc resistor 5 10 15 20 25 30 35 40 45 50 55 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 frequency (khz) rrosc (kohm) rrosc nominal spec figure 16 operational frequency vs rosc resistor soft start capacitor c ss/del the c ss/del capacitor programs four different time parameters, i.e. soft start delay time, soft start time, vr ready delay time and over-current fault latch delay time after vr ready. these parameters can be calculated with the following equations: 6 / / 10 * 5 . 52 4 . 1 * 4 . 1 * ? = = del ss chg del ss ssdelay c i c t (1) 6 / / 10 * 5 . 52 8 . 0 * * ? = = del ss chg del ss ss c i vref c t (2) 6 / / _ 10 * 5 . 52 32 . 2 * ) 12 . 3 ( * ? = ? = del ss chg del ss delay pg c i vref c t (3) . 10 * 5 . 52 10 * 120 * 10 * 120 * 6 3 / 3 / _ ? ? ? = = del ss chg del ss delay oc c i c t (4) ir3513z page 27 may 11, 2009 over current setting resistor r ocset the inductor dc resistance is utilized to sense the inductor current. the copper wire of the inductor has a constant temperature coefficient of 3850 ppm/c, and therefore the maximum inductor dcr can be calculated from (5). r l_max and r l_room are the inductor dcr value at maximum temperature (t l_max ) and room temperature (t_ room), respectively. )] ( 10 * 3850 1 [ _ 6 _ _ room max l room l max l t t r r ? ? + ? = ? (5) the total input offset voltage (v cs_tofst ) of current sense amplifier in phase ics is the sum of input offset (v cs_ofst) of the amplifier itself and that created by the amplifier input bias current flowing through the current sense resistor r cs . cs csin ofst cs tofst cs r i v v ? + = + _ _ (6) the over-current limit is set by the external resistor, r ocset, as defined in (7), where i limit is the required over current limit. i ocset, the bias current of ocset pin, changes wi th switching frequency set by resistor r osc and is determined by equation (9). g cs is the gain of the current sense amplifier. in a multiphase architecture the peak to peak ripple of the net inductor current is much smaller than the stand al one phase due to interleaving. the ratio of the peak to average current in this case can be approximated using (8). ocset cs tofst cs p max l limit ocset i g v k r n i r / ] ) 1 ( [ _ _ ? + + ? ? = (7) () ) 1 ( 2 / ) 1 ( ) ( ) 1 ( d d f l n i d n m n m d n d d v k sw limit i p ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? = (8) ) ( 600 ? = k rosc iocset (9) where i limit =maximum over current limit n=number of phases k p =ratio of the peak to average current for the inductor g cs =gain of the current sense amplifier i ocset = determined by the rosc and given (9) d=vo/v i m=maximum integer that doesn?t exceed (n*d) vout programming resistor r fb1 and r fb3 the feedback pin (fb) is connected to an external resistor divider to set the output voltage. the error amplifier has a 0.8 v reference (typical) and the output voltage is determined by selecting resistor divider values (see figure 1). 8 . 0 8 . 0 * 1 3 ? = vout r r fb fb (10) ir3513z page 28 may 11, 2009 vccl programming resistor r vcclfb1 and r vcclfb2 since vccl voltage is proportional to the mosfet gate driver loss and inversely proportional to the mosfet conduction loss, the optimum voltage should be chosen to maximize the converter efficiency. vccl linear regulator consists of an external npn transistor, a ce ramic capacitor and a programmable resistor divider. pre- select r vcclfb1 , and calculate r vcclfb2 from (11). 19 . 1 19 . 1 * 1 2 ? = vccl r r vcclfb vcclfb (11) vccl capacitor c vccl the capacitor is selected based on the stability requirement of the linear regulator and the load current to be driven. the linear regulator supplies the bias and gate drive current of the phase ics. a 4.7uf normally ensures stable vccl performance for most applications. vccl regulator drive resistor r vccldrv the drive resistor is primarily dependent on the load curr ent requirement of the linear regulator and the minimum input voltage requirements. the following equation gives an es timate of the average load current of the switching phase ics. c vccl phs vccl gt gb avg drive i n i n q q i _ _ _ ) 1 ( ) ( + ? ? + ? + = (12) q gb and q gt are the gate charge of the top and bottom fet, i vccl_phs is the vccl current of the phase ic-s, i vccl_c is the vccl current of the controller and n is the number of phases. for a minimum input voltage and a maximum vccl, the maximum r vccldrv required to use the full pull-down curr ent of the vccl driver is given by min _ / (max) 7 . 0 (min) avg drive i vccldrv i vccl v r ? ? = (13) due to limited pull down capability of the vccldrv pin, make sure the following condition is satisfied. ma r vccl v vccldrv i 10 (min) 7 . 0 (max) < ? ? (14) in the above equation, v i ( min) and v i ( max) is the minimum and maximum anticipated input voltage. if the above condition is not satisfied there is a need to use a device with higher min or darlington configuration can be used instead of a single npn transistor. inductor current sensing capacitor c cs and resistor r cs the dc resistance of the inductor is utilized to se nse the inductor current. usually the resistor r cs and capacitor c cs in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage across the capacitor c cs represents the inductor current. if the two time constants are not the same, the ac component of the capacitor voltage is different from that of the real inductor current. the time constant mismatch does not affect the average current sharing among the multiple phase s, but affects the current signal ishare. measure the inductance l and t he inductor dc resistance r l . pre-select the capacitor c cs and calculate r cs as follows. cs l cs c r l r = (15) ir3513z page 29 may 11, 2009 bootstrap capacitor c bst depending on the duty cycle and gate driv e current of the phase ic, a capacito r in the range of 0.1uf to 1uf is needed for the bootstrap circuit. decoupling capacitors for phase ic 0.1uf-1uf decoupling capacitors are requir ed at vcc and vccl pins of phase ics. over-voltage resistors r ov1 and r ov2 the over-voltage resistors are used to set the voltage at the ovsns pin. if the voltage of the ovsns pin exceeds vref by 85mv then the over-voltage protection will be ac tivated and the error amplifier voltage will be pulled down turning the converter off. the over-voltage fault is latched, which means that the power to the converter has to be recycled for the fault to clear. choose vovsns a certain value ? v below vref. vref is typically 0.8 v. the over- voltage threshold will then be ? v+85mv. select r ov1. r ov2 is calculated based on (16). vovsns v r vovsns r out ov ov ? = 1 2 * (16) vref slew rate programming capacitor c vref and resistor r vref the slew rate of margin down-slope can be programmed by the external capacitor c vref as defined in (17), where i sink is the sink current of the vref pin. the slew rate of margin up-slope is the same as that of down-slope. the resistor r vref is used to compensate the vref circuit and can be calculated as shown in (18). margin margin sink vref sr sr i c 6 10 * 132 ? = = (17) 2 15 10 2 . 3 5 . 0 vref vref c r ? ? + = (18) type iii compensation choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase, the desired phase margin c and rfb1 (see figure 17). determine the component values based on the equations below. wc is 2* *fc (the crossover angular frequency), le is the equivalent inductanc e of the converter, c is the output capacitance, rst is the total equivalent resistance in series with the inducto r, rc is the output capacitance esr and r is the load resistance. 1 1 rfb k ccp ? = (19) 1 1 wz ccp rcp ? = (20) 1 2 1 rfb wz cfb ? = (21) rcp wp ccp ? = 2 1 1 (22) ir3513z page 30 may 11, 2009 cfb wp rfb ? = 1 1 2 (23) where, 10 1 wc wz = (24) ) sin( 1 ) sin( 1 2 c c wc wz + ? ? = (25) ) sin( 1 ) sin( 1 1 c c wc wp ? + ? = (26) 1 4 . 1 2 wp wp ? = (27) r t t h gpwm rst r wc a wc b t wc t wc k ? ? ? ? + ? + ? ? ? + ? = 6 5 2 2 2 2 2 2 2 2 4 4 ) )( ) 1 )(( ( (28) where gpwm is the gain of the pwm generator , h is the gain of the feedback filter and r st r rc rst rc r rst r c le a + ? + ? + ? + = ) ( (29) r st r rc r c le b + + ? = (30) 2 1 1 2 1 wz wz wc t ? ? = (31) 2 1 1 2 2 wp wp wc t ? ? = (32) 2 1 1 1 3 wz wz t + = (33) 2 1 1 1 4 wp wp t + = (34) 2 2 2 2 2 2 5 ) ) 1 ( ( ) 1 ( a wc b c rc wc a c rc wc wc b t ? ? ? ? + ? ? ? + ? ? = (35) 2 4 3 2 2 1 2 2 4 1 3 2 4 6 ) ( ) ( t t wc t t wc t t t t wc t ? ? + ? + ? ? ? = (36) ir3513z page 31 may 11, 2009 3 1 2 - + cf b ccp1 ccp rf b2 rf b1 rcp vref eaout vo ut rf b3 figure 17 voltage loop compensation network ir3513z page 32 may 11, 2009 layout guidelines the following layout guidelines are recommended to reduce the parasitic inductance and resistance of the pcb layout, therefore minimizing the noise coupled to the ic. ? dedicate at least one middle layer for a ground plane. ? separate analog bus (eain, dacin and ishare) from digital bus (clkin, phsin, and phsout) to reduce the noise coupling. ? connect pgnd to lgnd pins to the ground plane through vias ? place current sense re sistors and capacitors (r cs and c cs ) close to ic. use kelvin connection for the inductor current sense wires, but separate the two wires by gr ound polygon. the wire from the inductor terminal to csin- should not cross over the fast transition nodes, i.e. switching nodes, gate drive outputs and bootstrap nodes. ? place the ic, gate drive side as close as possible to the mosfets to reduce the parasitic resistance and inductance of the gate drive paths. ? place the input ceramic capacitors close to the drain of top mosfet and the source of bottom mosfet. ? ? ir3513z page 33 may 11, 2009 pcb metal and component placement ? lead land width should be equal to nominal part lead width. the minimum lead to lead spacing should be 0.2mm to minimize shorting. ? lead land length should be equal to maximum part l ead length + 0.3 mm outboard extension + 0.05mm inboard extension. the outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. ? center pad land length and width should be equal to maximum part pad length and width. however, the minimum metal to metal spacing should be 0.17mm for 2 oz. copper ( 0.1mm for 1 oz. copper and 0.23mm for 3 oz. copper) ? four 0.30mm diameter vias shall be placed in the center of the pad land and connected to ground to minimize the noise effect on the ic. ? no pcb traces should be routed nor vias placed under an y of the 4 corners of the ic package. doing so can cause the ic to rise up from the pcb result ing in poor solder joints to the ic leads. ir3513z page 34 may 11, 2009 solder resist ? the solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. the solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all non solder mask defined (nsmd). theref ore pulling the s/r 0.06mm will always ensure nsmd pads. ? the minimum solder resist width is 0.13mm. ? at the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of 0.17mm remains. ? the land pad should be solder mask defined (smd), with a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist mis-alignm ent. in 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. ? ensure that the solder resist in-b etween the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip sepa rating the lead lands from the pad land. ? the four vias in the land pad should be tented or plugged from bottom board side with solder resist. ir3513z page 35 may 11, 2009 stencil design ? the stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. reducing the amount of solder deposited will minimize the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, the stenc il apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. ? the stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. ? the land pad aperture should be striped with 0.25mm wide openings and spaces to deposit approximately 50% area of solder on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open. ? the maximum length and width of the land pad stencil ap erture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. ir3513z page 36 may 11, 2009 applications package information 32l mlpq (5 x 5 mm body) ? ja = 22.4 o c/w, jc = 0.86 o c/w data and specifications subject to change without notice. this product has been designed and qualified for the consumer market. qualification standards can be found on ir?s web site. ir world headquarters: 233 kansas st., el segundo, califor nia 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . www.irf.com www.irf.com |
Price & Availability of IR3513ZMPBF
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |